Early Bird Registration Open Until Sept. 30 for Workshop on Practical Reproducibility in HPC!

Seats are limited; act now to reserve your spot!

Exciting news for the HPC community! Registration is now open for the Community Workshop on Practical Reproducibility in HPC, happening November 18, 2024, in Atlanta. Don't miss early bird pricing and the chance to engage with leading experts on this crucial topic. Learn more about keynotes, discussions, and how you can be part of shaping the future of reproducibility in HPC...

Towards Characterizing Genomics Workload Performance at Scale

Leveraging Chameleon's Bare Metal Resources to Benchmark Genomics Workflows

Martin Putra, a 4th year PhD student at the University of Chicago, shares how he used Chameleon to build and test a scalable benchmarking tool for genomics workflows, uncovering insights that could lead to more efficient resource management for these computationally intensive tasks.

Composable Hardware on Chameleon NOW!

Introducing new GigaIO nodes with A100 GPUs

Exciting news for Chameleon users! We're introducing GigaIO's composable hardware at CHI@UC and CHI@TACC. This innovative technology allows for flexible GPU configurations, supporting up to 8 GPUs per node. Learn how this new feature can enhance your research capabilities and improve hardware utilization. Discover the specifications and unique advantages of our new composable systems in this blog post.

Chameleon Changelog for July 2024

This month we celebrated 9 years of Chameleon, and shared the exciting news of Chameleon Phase 4! We also completed the openstack upgrade at CHI@UC, updated the Getting Started, and released a dev version of python-chi.

Chameleon Testbed Secures $12 Million in Funding for Phase 4

Expanding Frontiers in Computer Science Research

We are thrilled to announce that Chameleon, our experimental testbed for computer science research, has been awarded $12 million in funding from the U.S. National Science Foundation (NSF) for its fourth phase. Four more years of Chameleon!

Rethinking Memory Management for Multi-Tiered Systems

Exploring Efficient Page Profiling and Migration in Large Heterogeneous Memory

Explore the cutting-edge research of Professor Dong Li from UC Merced as he tackles the challenges of managing multi-tiered memory systems. Learn how his innovative MTM (Multi-Tiered Memory Management) system optimizes page profiling and migration in large heterogeneous memory environments. Discover how Chameleon's unique hardware capabilities enabled this groundbreaking experiment, and gain insights into the future of high-performance computing memory management. This blog offers a glimpse into the complex world of computer memory hierarchies and how researchers are working to make them more efficient and accessible.

Expanding Horizons with CHI@Edge: New Peripheral Support

Enhancing Edge Computing Research with Advanced Sensors and Cameras

This blog post introduces the latest advancements in peripheral support for the CHI@Edge research testbed. It highlights the platform's holistic approach to integrating a wide range of sensors and cameras, opening up new possibilities for edge computing experiments. The post covers recent updates to documentation and tutorials, showcasing specific peripherals like the Waveshare Sense HAT-B and the Pi Camera Module 3. It also provides real-world examples of edge computing applications in fields such as precision agriculture and marine biology. Researchers are guided through the process of utilizing these new capabilities, with links to comprehensive tutorials on GPIO, sensors, and camera …

Chameleon Changelog for June 2024

This month, we are preparing for a big upgrade on July 15th. Additionally, we have CHI-in-a-box for edge sites, new hardware at CHI@UC, and improvements to project management.

Real-time Scheduling for Time-Sensitive Networking: A Systematic Review and Experimental Study

Optimizing Network Performance with Chameleon's Computing Power

In this study, Chuanyu Xue tackles the complex challenge of optimizing Time-Sensitive Networking (TSN) for real-world applications. Using Chameleon's powerful computing resources, he conducts a comprehensive evaluation of 17 scheduling algorithms across 38,400 problem instances. This research not only sheds light on the strengths and weaknesses of various TSN scheduling methods but also demonstrates how large-scale experimentation can drive advancements in network optimization. Readers will gain insights from Xue's journey, including key findings, implementation challenges, and valuable tips for leveraging Chameleon in their own research.

Power Measurement and Management on Chameleon

Exploring Power Monitoring Techniques with RAPL, DCMI, and Scaphandre

Monitoring power consumption is crucial for understanding the energy efficiency of your applications and systems. In this post, we explore various techniques for measuring power usage on Chameleon nodes, including leveraging Intel's RAPL interface for fine-grained CPU and memory power data, utilizing IPMI's DCMI commands for system-level power information, and employing the Scaphandre tool for detailed per-process power monitoring and visualization. We provide practical examples and step-by-step instructions to help you get started with power measurement on Chameleon, enabling you to gain valuable insights into the energy footprint of your workloads.